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Simulation problem with F(1) macrocell on SLG46880V

2 months ago

Simulation problem with F(1) macrocell on SLG46880V

Posted by马修H.0 points 6 replies
0 upvotes

I'm using the F(1) computational macrocell on a SLG46880V device. It looks like when computations are performed using the cell on inputs coming from the dedicated analog comparator pins, and the outputs of the F(1) block are routed to the FSM transition inputs, the states don't transition correctly in the simulation.

当路由一般conne输入ction matrix it seems to work OK. Please see links to images and exaple file:

https://imgur.com/a/liAV0ZG

https://imgur.com/a/PkO0luS

https://www.dropbox.com/s/l8loe30ldw3pf7g/F%281%29%20error%20example.gp6?dl=0

2 months ago

ssaravan

Hi Matthew,

谢谢你伸出援手。F(1)计算宏小区将开始执行指令的唯一时间是当ASM Macrocell首次进入新状态时。(您还可以在数据表的F(1)宏单元部分中找到一些更有用的信息)

So when the input voltage is less than the reference volatge of the ACMP, the ACMP goes low and the F(1) block stops and ASM remains in State 0. Hence you donot see a transition. Could you please try using the Loop with Delay command in the command sequence in addition to OUT0? So that every time the iteration goes through the loop, the threshold is monitored and the there is a transition.

Please let me know if this helps

Kind Regards,

Shivani

2 months ago

马修H. 0 points

Ok Shivani I see what you mean. I will try adding the loop and see if it changes anything, thank you.

1 month ago

马修H. 0 points

嗨,希纳里再次。我仍然没有任何运气完成我正在尝试的事情,它是在Gven状态中连续监视模拟输入,使用F(1)宏电池执行运行计算,并且当a时触发状态转换满足某些计算条件。一个示例是通过与F(1)单元输入相关联的四个模拟比较器,使用堆栈机器的三位格雷码连持一个例子,然后在三位中的特定位时触发状态转换f(1)输出设置。对于f(1)代码,我有类似的东西:

LOAD4 //push LOAD4 input bit onto stack OUT2 //copy top bit of stack to OUT2, MSB LOAD2 //push LOAD2 input bit onto stack OUT1 //copy top bit of stack to OUT1, middle bit LOAD1 LOAD3 INV //invert top bit of stack, LOAD3 AND //top two bits on stack, push result back to top OUT0 //copy top bit to OUT0 PUSH0 //top bit of stack must be 0 to trigger loop instruction LOOP w DELAY // back to start

As you say without a loop statement the F(1) computation is only performed one time on entry to the state. With a loop & delay it looks like in simulation the stack machine enters an infinite loop, the outputs of the F(1) change continously but control is then never returned to the ASM and the transition never happens. Is it possible to do this? Do you have a working example you could share if so? Thank you

1 month ago

ssaravan

Hi Matthew,

Please find attached a working example of the F(1) macrocell. The command sequences are a bit different than yours

Kind Regards

Shivani

Attachment Size
ACMPs F(1).zip 8.47 KB

1 month ago

马修H. 0 points

Thank you for your example Shivani and sory for the delay in my reply, unfortunately the issue I'm experiencing still remains. The F(1) cell enters the loop and computes the 4-input AND of the ACMP inputs continuously not a problem in your example. However if I take say the OUT0 of the F(1) cell and connect it to a state transition input on the ASM it looks like it never triggers, the loop continues infinitely and control is never returned back to the ASM in that situation, where state transition inputs are only coming from the outputs of the F(1).

If I connect the OUT0 of the F(1) to both the ASM transition input and the "interrupt" pin on the F(1) then the transition is triggered when OUT0 goes high, I assume because control is returned back and the loop breaks out concurrently with the ASM recieving the transition signal, but this seems like a race hazard and not a partiuclarly useful configuration, anyway, as that connection then persists across all states and all four possible F(1) configurations. I'm assuming this is correct behavior though, once the F(1) enters an infinite loop in a particular state the only way to break out is via an external input to the ASM or using the interrupt pin to force a return of control to the ASM?

1 month ago

ssaravan

Hi Matthew,

I see what you mean. Could you maybe try using a delay block to connect the OUT0 to the ASM? Perhaps like a One shot delay or even better a DFF, so that you donot enter a race condition

Kind Regards

Shivani