Capacitor Selection Criteria

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电子记事本
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Capacitor Selection Criteria

I am interested in using the DA9062 PMIC for a Zynq 7010 product. The data sheet has recommendations for capacitors, but I did not see much information about the requirements for them, such as min/max capacitance, package size, quantity, ESR, ESL, etc. The datasheet says"When selecting a capacitor, especially ones with high capacitance and small size, the DC bias characteristic has to be taken into account". I understand what DC bias is, so this suggests it is possible to use alternate components than those recommended. But I would like to understand what the limitations are.

是否选择了推荐的元件来说明PCB布局有多小?或者选择它们是因为较小的封装尺寸会有较低的安装电感?是否同时使用多种成分以进一步降低ESR和ESL?还是使用了多个较小的值来灵活地减少生产中使用的电容器数量?是否有最大容量可供使用?

Xilinx recommends certain values for the Zynq 7010, such as 100uF for bulk capacitance. If possible I would like to use the same capacitors for the PMIC regulators. I have 100uF 1206 capacitors, which I hope will work well because capacitors are very hard to procure these days!

谢谢,

电子记事本

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Hello ElectronHerder,

Hello ElectronHerder,

Let me talk with the team and get back to you.

Kind regards,
Elliott Dexter

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Hello ElectronHerder,

Hello ElectronHerder,

We state in the DA9062 datasheet the tolerances for Capacitor's, ESR and Inductors (I have attached an example image), they can be found in the electrical characteristics part of the datasheet. Some of these parameters are not listed in the "component selection" section; this section is for specific recommended components. The components we recommend have been chosen for a small PCB sizem whilst maintining performance.

Kind regards,
Elliott Dexter

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电子记事本
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谢谢你埃利奥特的指点

谢谢你埃利奥特的指点that out. I'm sorry I didn't see it. In the past I have used a lot of Texas Instruments parts, and their data sheets usually have a section on component selection that includes formulas and a description of the limitations. I guess I'm a creature of habit, and didn't think to look in the in the Electrical Characteristics section.

输出电容要求是否基于满载?例如,如果Buck 1在全电流模式下工作,但只驱动1.25A的最大值,所需的电容会更小吗?我不是要具体的数字,只是一个概括。与满足最小纹波规格相比,稳定性需要多少电容?

Why is there a max spec for the output capacitor? What happens when you have too much capacitance? Does it become unstable? The regulator will be supplying current to a circuit that includes a significant amount of decoupling capacitance, so I am assuming that this must only be referring to the capacitors that are physically very close to the inductor.

Here is a link to the data sheet for the 100uF capacitor that I am using:

http://www.samsungsem.com/kr/support/product-search/mlcc/__icsFiles/afie...

我不确定如何应用ESR图the DA9062 ESR spec. The spec says "f > 100 kHz", which I take to mean all frequencies above 100 kHz. Is that right? I'd say this capacitor is pretty close to meeting the spec at 100 MHz. I believe your reference design uses two capacitors in parallel to halve the ESR and impedance. If I use this capacitor do you see any issues? How much benefit is there in using two capacitors in parallel?

谢谢并致以最诚挚的问候,

电子记事本

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Hello ElectronHerder,

Hello ElectronHerder,

The recommend output capacitance is based upon full load. That’s why we have listed two different sets of recommended capacitors and their tolerances. Please see attached diagram for an example.

The main effect of increasing the output capacitance of the buck converter beyond the recommended maximum capacitance value would be an increase in buck start-up time and effect the slew rate. I cannot see why using 1 x 100 uF over 2 x 47 uF would greatly affect the start-up time. We chose to use two capacitors in parallel instead of one capacitor to reduce ESR, if the capacitor you plan on using is similar to our spec ESR then it should be ok.

电容器看起来没问题,但是你发给我的链接没有ESR过热。

Kind regards,

Elliott Dexter

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谢谢你,艾略特。我没有

谢谢你,艾略特。我不确定你的回答是否准确地回答了我的问题。这两组电容值适用于设备的两种不同操作模式。在半电流模式下,一半的通过设备被禁用,这意味着输出阻抗不同于全电流模式。我很好奇,在全电流模式下,电容器的要求是什么,但最大负载是电位电流的一半。有时我会问一些不切实际的问题来帮助我理解事情是如何运作的。

Your answer about the main effect of increasing the output capacitance was enlightening. It appears the sequencing of the PMIC is based on time, not whether a voltage of one supply has been reached before starting the next supply. Kind of "open loop" instead of "closed loop". Is that a fair way to describe it?

Thank you for looking at the data sheet for the capacitor. I will see if I can find more data on ESR over temperature.

Kind regards,

电子记事本

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